In double data rate fourth generation (DDR4) and fifth generation (DDR5) and other SerDes data communication, a memory interface (i.e., a registered clock driver or a data buffer) is a source of synchronous data transportation between the host central processing unit (CPU) and the synchronous dynamic random-access memory (SDRAM) modules. The source sync input clock and data are received and transmitted through the I/O pad. Through the clock path, more and more skew will be accumulated due to delay variation or mismatch. Furthermore, jitter will be accumulated from the thermal noise of various devices or system noise such as duty cycle variation, supply noise and spurs associated with the operating frequencies.
Conventional approaches to reduce jitter involve tuning and trimming the skew for each path to keep the skew within the specification margin. The amount of jitter is critical to the clock since the data rate is above 4.4 GHz. The tuning and trimming causes so much extra effort for the bench and Automatic Test Equipment (ATE) validation. Controlling the jitter is becoming more challenging with designs moving to DDR5.
It would be desirable to implement standing and resonant wave clocking in DDR RCD and data buffer.